List of practical | A-Div. Enrollment no. | B-Div. Enrollment no. | B-Div. Enrollment no. |
To study and verify the Truth Tables of AND, OR, NOT, NAND, NOR EXOR logic gates | 140140109001 to 5 | 140140109064 to 70 | 150143109011 to 9015 |
Design and verify the logic circuit of Half adder using logic gates. | 140140109006 to 10 | 140140109071 to 75 | 150143109016 to 9020 |
Design and verify the logic circuit Full adder using of Half adder | 140140109011 to 15 | 140140109076 to 81 | 150143109022 to 9025 |
Design and verify the logic circuit of Half subtractor using logic gates. | 140140109016 to 20 | 140140109082 to 86 | 150143109026 to 9029 |
Design and verify the logic circuit Full subtractor using of Half subtractor | 140140109021 to 25 | 140140109087 to 91 | |
To Design and verify the truth table of code conversion from binary to gray code (4 bit) using basic Logic Gates | 140140109026 to 30 | 140140109092 to 96 | |
To Design and verify the truth table of code conversion from gray to binary code (4 bit) using basic Logic Gates | 140140109031 to 35 | 140140109097 to 101 | |
To Design and verify the Truth Table of 3-bit Parity Generator and 4-bit Parity Checker using basic Logic Gates with an even parity bit | 140140109036 to 40 | 140140109102 to 106 | |
To Design and verify the truth table of code conversion from BCD to Excess-3 using basic Logic Gates | 140140109041 to 45 | 140140109108 to 112 | |
To the Truth Table of 4:1 Multiplexer using IC 74153 | 140140109046 to 50 | 140140109113 to 117 | |
To the Truth Table of 1:4 Demultiplexer using IC 74139 | 140140109051 to 55 | 140140109118 to 123 | |
To design the 8:1 MUX using two 4:1 MUX | 140140109056 to 60 | 150143109001 to 9005 | |
To Design and verify the truth table of J K Flip flop using IC 7473 | 140140109061 to 63, 130140109064 | 150143109006 to 9010 | |
Note: | |||
1. All the students are instructed to complet the project with the assign group. | |||
2. The last date for the project completion is 20/02/2016. | |||
3. If necessory take guidance of respective sub. Teacher. | |||
4. The lab. Manual for the sub. Is already circulated amongs the students. | |||
DRD/PKS |
Friday, 29 January 2016
List of practical and working model assign to students of sem. 4. ( Digital Electronics)
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